The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device that uses a ferroelectric film.
Semiconductor devices such as DRAMs and SRAMs are used extensively in various information processing apparatuses including computers as a high-speed main memory device. These conventional semiconductor devices, however, are volatile in nature and the information stored therein is lost when the electric power is turned off. Thus, it has been practiced in conventional computers and computer systems to use a magnetic disk device as a large capacity, auxiliary storage device for storing programs and data.
However, magnetic disk devices are bulky and fragile, and are inherently vulnerable to mechanical shocks. Further, magnetic disk devices generally have drawbacks of large electrical power consumption and low access speed.
In view of the problems noted above, there is an increasing tendency in computers and computer systems of using flash-memory devices for the non-volatile auxiliary storage device. A flash-memory device is a device having a construction similar to a MOS transistor and stores information in a floating gate in the form of electrical charges. It should be noted that flash-memory devices have a construction suitable for monolithic integration on a semiconductor chip in the form of an LSI. Thus, there are attempts to construct a large-capacity storage device comparable to a magnetic disk device by using a flash-memory.
In a flash-memory device, writing of information is achieved by tunneling of hot electrons through a tunneling insulation film into the floating gate electrode. Further, erasing of the information is achieved also by causing the electrons in the floating gate to tunnel to a source region or to a channel region through the tunneling insulation film. Thus, a flash-memory device has an inherent drawback in that it takes a substantial time for writing or erasing information. Further, a flash-memory device generally shows the problem of deterioration of the tunneling insulation film after a repeated writing and erasing operations. When the tunneling insulation film is deteriorated, the reading or erasing operation becomes unstable and unreliable. An EEPROM, having a similar construction to a flash-memory, has a similar problem.
In view of the various drawbacks of the foregoing conventional non-volatile semiconductor devices, there is a proposal of a ferroelectric semiconductor memory device designated hereinafter as FeRAM for the auxiliary memory device and further for the high-speed main memory device of a computer. A ferroelectric semiconductor memory device stores information in a ferroelectric capacitor insulation film in the form of spontaneous polarization.
A ferroelectric semiconductor memory device typically includes a memory cell transistor and a memory cell capacitor similarly to a DRAM, wherein the memory cell capacitor uses a ferroelectric material such as PZT (Pb(Zr,Ti)O3) or PLZT ((Pb,La)(Zr,Ti)O3) for the capacitor insulation film. Thus, the ferroelectric semiconductor memory device is suitable for monolithic integration to form an LSI.
As the ferroelectric semiconductor memory device carries out the writing of information by controlling the spontaneous polarization of the ferroelectric capacitor insulation film, the writing is achieved with a high speed, faster by a factor of 1000 or more than in the case of a flash-memory. As noted before, the writing of information is achieved in a flash-memory by injecting hot electrons into the floating gate through the tunneling insulation film. As the control of the polarization is achieved by applying a voltage, the power consumption is also reduced below about {fraction (1/10)} as compared with the case of a flash-memory. Further, the ferroelectric semiconductor memory device, lacking the tunneling insulation film, provides an increased lifetime of one hundred thousand times as large as the lifetime of a flash-memory device.
Currently, FeRAMs are fabricated according to the relatively easy design rule of about 1 xcexcm. On the other hand, investigation is being made for increasing the tightness of the design rule so as to enable integration of the FeRAMs with other high-speed submicron devices such as CMOS logic devices on a common semiconductor chip.
FIG. 1 shows the construction of a conventional FeRAM 10.
Referring to FIG. 1, the FeRAM 10 includes a memory cell transistor constructed on a p-type Si substrate 11, on which an active region is defined by a field oxide film 12. On the Si substrate 11, there is provided a gate electrode 13 in correspondence to the foregoing active region, wherein the gate electrode 13 constitutes the word line of the FeRAM. Further, a gate oxide film not illustrated is interposed between the Si substrate 11 and the gate electrode 13, and diffusion regions 11A and 11B of the n+-type are formed in the substrate 11 at both lateral sides of the gate electrode 13 as the source region and the drain region of the memory cell transistor. Thereby, a channel region is formed in the substrate 11 between the diffusion region 11A and the diffusion region 11B.
It should be noted that the gate electrode 13 is covered by a CVD oxide film 14 provided so as to cover the surface of the Si substrate 11 in correspondence to the active region, wherein the CVD oxide film 14 is covered by a planarizing interlayer insulation film 15. The interlayer insulation film 15 is formed with a contact hole 15A exposing the diffusion region 11B, and the contact hole 15A is filled by a conductive plug 16 of polysilicon or WSi.
Further, there is provided an adhesion layer 17 having a Ti/TiN structure on the interlayer insulation film 15 so as to cover the exposed part of the plug 16, and a lower electrode 18 of Pt is formed on the foregoing adhesion layer 17. The lower electrode 18 is covered by a ferroelectric capacitor insulation film 19 of PZT or PLZT, and an upper electrode of Pt is formed on the ferroelectric capacitor insulation film 19.
It should be noted that the lower electrode 18, ferroelectric capacitor insulation film 19 and the upper electrode 20 form together a ferroelectric capacitor defined by a side wall, wherein the side wall is covered by a CVD oxide film 21, and the ferroelectric capacitor as a whole is covered by another interlayer insulation film 22.
The interlayer insulation film 22 is formed with a contact hole 22A exposing the diffusion region 11A, and there is provided a bit line pattern 23 of Al or an Al-alloy on the interlayer insulation film 22 so as to make an electrical contact with the diffusion region 11A at the contact hole 22A.
FIG. 2 shows the hysteresis appearing in the polarization of a PLZT film constituting the foregoing ferroelectric capacitor insulation film 19.
Referring to FIG. 2, it will be noted that the PLZT film 19 experiences an inversion of polarization when a predetermined write voltage is applied between the lower electrode 18 and the upper electrode 20 such that a predetermined electric field is applied to the PLZT film 19. In other words, desired information is written into the PLZT film 19 in the form of binary data by applying the write voltage across the upper electrode 20 and the lower electrode 18. Further, the reading of the information thus written into the PLZT film 19 is achieved by detecting the conduction or no-conduction of the memory cell transistor, wherein such a detection is made by activating the foregoing word line, and hence the gate electrode 13, and further by detecting the voltage appearing at the bit line electrode 23.
Larger the value of the spontaneous polarization represented in FIG. 2 by 2Pr, the more the reliability of the retention of information in the PLZT film 19. Further, the magnitude of the electric field needed to cause a writing of information decreases with increasing value of 2Pr. In other words, increase of the spontaneous polarization 2Pr contributes to the decrease of the drive voltage of the FeRAM 10. Thus, there is a demand for increasing the value of the spontaneous polarization 2Pr in the FeRAM 10 of FIG. 1.
It should be noted that the semiconductor memory device of FIG. 1 can be used also for a DRAM. In this case, due to the very large relative dielectric constant of the ferroelectric capacitor insulation film 19, a sufficient capacitance is secured without using a complicated shape and process for forming the memory cell capacitor.
Meanwhile, it is known that the PZT or PLZT film constituting the ferroelectric capacitor insulation film 19 of FIG. 1 shows a columnar microstructure and that the value of the spontaneous polarization 2Pr is maximized when the crystal grains therein are oriented in the  less than 111 greater than  direction.
Thus, there have been various attempts to align the crystal grains in the ferroelectric capacitor insulation film 19 in the  less than 111 greater than  direction. For example, it is proposed to introduce Ar atoms into the lower electrode 18 by an ion implantation process so as to change the state of the lower electrode 18 into amorphous state (Japanese Laid-Open Patent Publication 5-543345). According to this prior art process, the lower electrode 18 then is subjected to a rapid thermal annealing (RTA) process. Alternatively, there is proposed to anneal the lower electrode 18 in a furnace before depositing the ferroelectric film 19 thereon (Nakamura, T., et al., Jpn. J. Appl. Phys. vol.34, pp.5184-5187). Further, there is an attempt to deposit the lower electrode 18 at a high temperature so as to enable the orientation of the crystal grains in the ferroelectric capacitor insulation film 19.
Unfortunately, the foregoing approach to convert the lower electrode 18 once into amorphous phase and then to cause a crystallization by an RTA process is ineffective for achieving a satisfactory degree of crystallization in the lower electrode 18, and no desirable crystal orientation is obtained in the ferroelectric capacitor insulation film 19. Further, when a high-temperature thermal annealing process is applied to the lower electrode 18 in a furnace, there is a tendency that the hillock phenomenon is induced in the lower electrode 18, wherein such a hillock caused in the lower electrode 18 decreases the yield of the semiconductor device.
In the formation of the ferroelectric capacitor as noted above, it is very important to crystallize the ferroelectric capacitor insulation film 19 by conducting a crystallization process. Further, it is also very important to control the process of forming the upper electrode 20. Without such a crystallization process, no desirable property is obtained for the ferroelectric capacitor.
Conventionally, such a ferroelectric capacitor is formed first by forming the adhesion layer 17 of the Ti/TiN structure and then the lower electrode 18 of Pt by a sputtering process conducted on the interlayer insulation film 15 in a reducing or inert atmosphere. Next, the ferroelectric capacitor insulation film 19 of PZT is formed on the lower electrode 18 by a sputtering process. By forming the lower electrode 18 in a reducing atmosphere or inert atmosphere, the problem of oxidation of the lower electrode 18 and associated problem of increase of the resistance are successfully avoided.
Next, the ferroelectric capacitor insulation film 19 is subjected to a thermal annealing process in an oxidizing atmosphere at a temperature of typically 700-800xc2x0 C., and the ferroelectric capacitor insulation film 19 thus formed undergoes a crystallization. Thereby, it has been practiced to conduct the crystallization process in an oxidizing atmosphere so that the formation of oxygen defects in the ferroelectric capacitor insulation film 19, caused as a result of diffusion of oxygen atoms from the ferroelectric capacitor insulation film 19 to the lower electrode 18, is successfully compensated for. As a result of the crystallization, the ferroelectric capacitor insulation film 19 shows a preferable hysteresis as represented in FIG. 2, with a spontaneous polarization 2Pr.
After the formation of the ferroelectric capacitor insulation film 19, the upper electrode 20 is formed on the film 19 by a deposition of Pt. Thereby, the deposition of the upper electrode 20 has been conducted in an inert atmosphere such as Ar so as to avoid the oxidation of Pt constituting the upper electrode 20.
On the other hand, in such a process of forming the upper electrode 20 on the ferroelectric capacitor insulation film 19 in an inert atmosphere, it is inevitable that the oxygen atoms in the ferroelectric capacitor insulation film 19 are extracted to some extent by the upper electrode 20, resulting in the formation of oxygen deficiency in the ferroelectric capacitor insulation film 19. It should be noted that the existence of the oxygen deficiency in the ferroelectric capacitor insulation film 19 tends to induce a diffusion of Pt from the upper electrode 20 into the ferroelectric capacitor insulation film 19, and there is caused a mutual diffusion of Pt and oxygen between the ferroelectric capacitor insulation film 19 and the upper electrode 20. When such a mutual diffusion is caused, the ferroelectric capacitor insulation film 19 shows a deterioration in the fatigue characteristic and the retention characteristic.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device having a ferroelectric or high-dielectric capacitor wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a ferroelectric capacitor and a semiconductor device having such a ferroelectric capacitor wherein the grain orientation in a ferroelectric capacitor insulation film forming the ferroelectric capacitor is controlled for maximum relative dielectric constant.
Another and more specific object of the present invention is to provide a ferroelectric capacitor and a semiconductor device having such a ferroelectric capacitor wherein the degradation of performance of the capacitor associated with the formation of the capacitor electrode is successfully avoided.
Another object of the present invention is to provide a high-dielectric capacitor and a semiconductor device having such a high-dielectric capacitor wherein the degradation of performance of the capacitor associated with the formation of the capacitor electrode is successfully avoided.
Another object of the present invention is to provide a fabrication process of a semiconductor device having a ferroelectric capacitor, comprising the steps of:
forming a lower electrode on a substrate;
applying a rapid thermal annealing process to said lower electrode;
depositing, after said step of rapid thermal annealing process, a ferroelectric film on said lower electrode;
crystallizing said ferroelectric film by applying a thermal annealing process to said ferroelectric film; and
forming an upper electrode on said ferroelectric insulation film.
Another object of the present invention is to provide a fabrication process of a ferroelectric capacitor, comprising the steps of:
forming a lower electrode on a substrate;
applying a rapid thermal annealing process to said lower electrode;
depositing, after said step of rapid thermal annealing process, a ferroelectric film on said lower electrode;
crystallizing said ferroelectric film by applying a thermal annealing process to said ferroelectric film; and
forming an upper electrode on said ferroelectric insulation film.
Another object of the present invention is to provide a ferroelectric capacitor, comprising:
a substrate;
a lower electrode formed on said substrate;
a ferroelectric film formed on said lower electrode; and
an upper electrode formed on said ferroelectric film,
said ferroelectric film comprising crystal grains aligned substantially in a  less than 111 greater than direction.
According to the present invention, Ti migrates from an adhesion layer formed underneath said lower electrode to the surface thereof in the form of TiOx as a result of the rapid thermal annealing process applied to the lower electrode. Thereby, TiOx thus migrated functions as nuclei of crystal growth and the ferroelectric crystals of the ferroelectric film, which may either of PZT, PLZT, BST or SBT, deposited on the lower electrode grows generally in the  less than 111 greater than  direction. Because of the  less than 111 greater than  orientation of the ferroelectric film, the spontaneous polarization is of the ferroelectric film is maximized. By conducting the thermal annealing process of the lower electrode only for a short time in the form of RTA, the oxidation of the lower electrode is avoided successfully. Further, the formation of unwanted hillock is avoided successfully.
Another object of the present invention is to provide a fabrication process of a semiconductor device having a capacitor, comprising the steps of:
forming a lower electrode;
depositing a dielectric film having a perovskite structure on said lower electrode;
crystallizing said dielectric film by applying a thermal annealing process to said dielectric film in an oxidizing atmosphere; and
forming an upper electrode, after said step of crystallizing, on said dielectric film,
said step of forming said upper electrode being conducted in an oxidizing atmosphere.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate;
a memory cell transistor formed on said substrate;
a memory cell capacitor in electrical contact with a diffusion region of said memory cell transistor,
said memory cell transistor comprising:
a lower electrode in electrical contact with said diffusion region;
a capacitor dielectric film having a perovskite structure formed on said lower electrode; and
an upper electrode of Pt formed on said capacitor dielectric film,
said upper electrode having a sputter etching rate substantially lower than a sputter etching rate of said upper electrode in the case said upper electrode is formed in a substantially inert atmosphere.
Another object of the present invention is to provide a fabrication process of a capacitor, comprising the steps of:
forming a lower electrode;
depositing a dielectric film having a perovskite structure on said lower electrode;
crystallizing said dielectric film by applying a thermal annealing process in an oxidizing atmosphere; and
forming, after said step of crystallizing, an upper electrode on said dielectric film,
wherein said step of forming said upper electrode is conducted in an oxidizing atmosphere.
According to the present invention, the upper electrode experiences a densification as a result of the step of forming the upper electrode in the oxidizing atmosphere. Thereby, the problem of oxygen diffusion from the dielectric film into the upper electrode is successfully avoided. The capacitor of the present invention shows a substantial improvement in terms of fatigue, retention, imprint and resistance against exfoliation.
Another object of the present invention is to provide a fabrication process of a semiconductor device having a capacitor, comprising the steps of:
forming a lower electrode;
depositing a dielectric film having a perovskite structure on said lower electrode;
crystallizing said dielectric film by applying a thermal annealing process in an inert atmosphere;
applying, after said step of crystallizing, a thermal annealing process to said dielectric film in an oxidizing atmosphere; and
forming, after said step of thermal annealing process in said oxidizing atmosphere, an upper electrode on said dielectric film.
Another object of the present invention is to provide a fabrication process of a capacitor, comprising the steps of:
forming a lower electrode;
depositing a dielectric film having a perovskite structure on said lower electrode;
crystallizing said dielectric film by applying a thermal annealing process in an inert atmosphere;
applying, after said step of crystallizing, a thermal annealing process to said dielectric film in an oxidizing atmosphere; and
forming, after said step of thermal annealing process in said oxidizing atmosphere, an upper electrode on said dielectric film.
Another object of the present invention is to provide a fabrication process of a semiconductor device having a capacitor, comprising the steps of:
forming a lower electrode;
depositing a high-dielectric film on said lower electrode;
crystallizing said high-dielectric film by applying thereto a thermal annealing process in an inert atmosphere;
applying, after said step of crystallizing, a thermal annealing process to said high-dielectric film in an oxidizing atmosphere; and
forming, after said step of applying said thermal annealing process in said oxidizing atmosphere, an upper electrode on said dielectric film,
wherein said thermal annealing process in said oxidizing atmosphere is conducted at a temperature set so that no substantial oxidation occurs in said lower electrode.
According to the present invention, the lower electrode experiences densification without substantial oxidation, by conducting the crystallization process in the inert atmosphere. As a result, the problem of mutual diffusion of the elements at the interface between the lower electrode and the dielectric or high-dielectric film is successfully minimized, and the capacitor leakage current, caused by the defects in the dielectric film acting as a carrier, is substantially reduced. As the crystallization process of the dielectric or high-dielectric film is conducted in the inert atmosphere separately from the oxidizing process for compensating for the oxygen deficiency of the dielectric or high-dielectric film, it becomes possible to increase the crystallization temperature and the relative dielectric constant of the dielectric or high-dielectric film is successfully maximized. Further, by conducting the thermal annealing process in the oxidizing atmosphere at the temperature in which no substantial oxidation is caused in the lower electrode, the problem of defect formation in the lower electrode is eliminated and the capacitor leakage current is reduced further.
Another object of the present invention is to provide a fabrication process of a capacitor, comprising the steps of:
forming a lower electrode;
depositing a dielectric film having a perovskite structure on said lower electrode;
raising the temperature of said dielectric film to a thermal annealing temperature while holding said dielectric film in an inert atmosphere;
changing, after said thermal annealing temperature is reached, the atmosphere of said dielectric film from said inert atmosphere to an oxidizing atmosphere while holding said dielectric film at said thermal annealing temperature;
annealing, after said step of changing the atmosphere, said dielectric film in said oxidizing atmosphere while holding said dielectric film at said thermal annealing temperature; and
forming, after said annealing step in said oxidizing atmosphere, an upper electrode on said dielectric film.
According to the present invention, the lower electrode undergoes densification as a result of the rapid temperature rise to the thermal annealing temperature in the inert atmosphere. As a result of the densification, the lower electrode experiences minimum oxidation when the thermal annealing process is conducted in the oxidizing atmosphere. The dielectric film thus processed have the crystal grains aligned in the  less than 111 greater than  direction.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.